Computer aids for VLSI design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Analog Device-Level Layout Automation
Analog Device-Level Layout Automation
A layout-aware synthesis methodology for RF circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The rectangle placement language
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
ALI: A procedural language to describe VLSI layouts
DAC '82 Proceedings of the 19th Design Automation Conference
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dive Into Python
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fast and accurate parasitic capacitance models for layout-aware
Proceedings of the 41st annual Design Automation Conference
Placement constraints in floorplan design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog layout synthesis: what's missing?
Proceedings of the 19th international symposium on Physical design
Analog Layout Synthesis: A Survey of Topological Approaches
Analog Layout Synthesis: A Survey of Topological Approaches
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Integrated Layout-Synthesis Approach for Analog ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Constraint-Based Layout-Driven Sizing of Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area optimization on fixed analog floorplans using convex area functions
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents the layout description script (LDS), which is a domain specific language intended to code layout templates to be used for layout-aware circuit synthesis. LDS supports both sequential and constraint programming and is suitable for both manual coding and automatic code generation. LDS is compared with previous approaches related to layout description. Code samples are given for alignment, abutment, symmetry, and similar constraints. Also, implementation of the LDS compiler is discussed and a methodology for handling complex constraints is presented. Due to its support for constraint programming, it is possible to constrain topological representations and even combine them. It is also possible to combine and constrain placement and routing in an LDS template. Finally, a capture tool has been implemented. This tool is designed to extract a template from an expert-drawn layout. Capture converts a data structure extracted through a guided user interface into a template. This tool highlights the compatibility of LDS with electronic design automation.