An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
A Skill-based library for retargetable embedded analog cores
Proceedings of the conference on Design, automation and test in Europe
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
A layout-aware synthesis methodology for RF circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
GA-SVM feasibility model and optimization kernel applied to analog IC design automation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Analog placement based on novel symmetry-island formulation
Proceedings of the 44th annual Design Automation Conference
Analog placement based on hierarchical module clustering
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Analog layout generator for CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog circuits optimization based on evolutionary computation techniques
Integration, the VLSI Journal
Analog layout synthesis: what's missing?
Proceedings of the 19th international symposium on Physical design
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques
Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Analog Layout Synthesis: A Survey of Topological Approaches
Analog Layout Synthesis: A Survey of Topological Approaches
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Module packing based on the BSG-structure and IC layout applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Integrated Layout-Synthesis Approach for Analog ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Constraint-Based Layout-Driven Sizing of Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Routing analog ICs using a multi-objective multi-constraint evolutionary approach
Analog Integrated Circuits and Signal Processing
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
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This paper describes an innovative analog IC layout generation tool, LAYGEN II, based on evolutionary computation techniques. The designer provides the high level layout guidelines through an abstract layout template. The template contains placement and routing constrains independently from technology, and can be used hierarchically in the definition of templates for complex circuits. LAYGEN II uses this expert knowledge to guide the evolutionary optimization kernels during the automatic layout generation in the target technology. The routing task of the proceeding can range from a template-based approach to a full automatic generation, if only connectivity is provided. The LAYGEN II tool is demonstrated for the layout generation of two typical analog circuit structures and the results validated by Calibre® design rule check tool.