Device-level placement for analog layout: an opportunity for non-slicing topological representations
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Modeling non-slicing floorplans with binary trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Placement constraints in floorplan design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Aladin: A Layout Synthesys Tool for Analog Integrated Circuits
Analog Integrated Circuits and Signal Processing
Placement with symmetry constraints for analog layout design using TCG-S
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Improved method of cell placement with symmetry constraints for analog IC layout design
Proceedings of the 2006 international symposium on Physical design
Analog placement with symmetry and other placement constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analog placement based on novel symmetry-island formulation
Proceedings of the 44th annual Design Automation Conference
Analog placement with common centroid constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Symmetry-aware placement with transitive closure graphs for analog layout design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Constraint-free analog placement with topological symmetry structure
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Symmetry constraint based on mismatch analysis for analog layout in SOI technology
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
An improved particle swarm optimizer for placement constraints
Journal of Artificial Evolution and Applications - Particle Swarms: The Second Decade
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Analog placement with common centroid and 1-D symmetry constraints
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog layout synthesis: recent advances in topological approaches
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Regularity-oriented analog placement with diffusion sharing and well island generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Regularity-constrained floorplanning for multi-core processors
Proceedings of the 2011 international symposium on Physical design
Placement constraints and macrocell overlap removal using particle swarm optimization
ANTS'06 Proceedings of the 5th international conference on Ant Colony Optimization and Swarm Intelligence
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
Proceedings of the International Conference on Computer-Aided Design
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Performance-driven analog placement considering monotonic current paths
Proceedings of the International Conference on Computer-Aided Design
Double patterning lithography-aware analog placement
Proceedings of the 50th Annual Design Automation Conference
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
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This paper addresses the problem of device-level placement for analog layout, focusing mainly on symmetry-related aspects. Different from most of the existent analog placement approaches, employing basically simulated annealing optimization algorithms operating on flat (absolute) spatial representations, our model uses a more recent topological representation called sequence-pair, which has the advantage of not being restricted to slicing floorplan topologies. In this paper, we explain how specific features essential to analog placement, such as the ability to deal with complex symmetry constraints (for instance, an arbitrary number of symmetry groups of cells), can be easily handled by employing the sequence-pair representation. Several analog examples substantiate the effectiveness of our placement tool, which is already in use in an industrial environment