A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Single step current driven routing of multiterminal signal nets for analog applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Performance-Driven Placement Algorithm with Simultaneous Place&Route Optimization for Analog IC's
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Signal-path driven partition and placement for analog circuit
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Current-driven wire planning for electromigration avoidance in analog circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Analog placement based on symmetry-island formulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven analog placement considering boundary constraint
Proceedings of the 47th Design Automation Conference
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A corner stitching compliant B*-tree representation and its applications to analog placement
Proceedings of the International Conference on Computer-Aided Design
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
Proceedings of the International Conference on Computer-Aided Design
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Routability-driven placement algorithm for analog integrated circuits
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Non-uniform multilevel analog routing with matching constraints
Proceedings of the 49th Annual Design Automation Conference
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symmetry within the sequence-pair representation in the context of placement for analog design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-Driven Analog Placement Considering Device Matching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Maze routing algorithms with exact matching constraints for analog and mixed signal designs
Proceedings of the International Conference on Computer-Aided Design
Performance-driven analog placement considering monotonic current paths
Proceedings of the International Conference on Computer-Aided Design
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Current-flow and current-density are two major considerations for placement and routing of analog layout synthesis. The current-flow constraints are specified to the critical nets with monotonic current/signal paths to reduce parasitic impacts. The current-density constraints are usually specified on the nets with variable wire widths to avoid the IR-drop and electromigration problems. In this paper, we propose the first work to simultaneously consider current-flow and current-density constraints while placing and routing the analog circuits with minimized chip area, routed wirelength, bend numbers, via counts, and coupling noise at the same time. We first present an enhanced B*-tree representation to simultaneously model modules and interconnects for an analog circuit. Then a simultaneous placement and routing algorithm is presented to generate a layout while satisfying the current-flow and current-density constraints with minimized chip area, routed wire-length, bend numbers, via counts, and coupling noise. Experimental results show that our approach can obtain better layout results and satisfy all specified constraints while optimizing circuit performance.