Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full-Chip Routing Considering Double-Via Insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint-based channel routing for analog and mixed analog/digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Simultaneous analog placement and routing with current flow and current density considerations
Proceedings of the 50th Annual Design Automation Conference
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Efficient analog layout prototyping by layout reuse with routing preservation
Proceedings of the International Conference on Computer-Aided Design
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Symmetry, topology-matching, and length-matching constraints are three major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. Topology-matching constraints are commonly imposed on critical yet asymmetry nets with the same number of bends, vias, and wirelength. Length-matching constraints are specified to route the nets which have limited resources with the same wirelength. These three constraints can reduce current mismatches and unwanted electrical effects between two critical nets. In this paper, we propose the first work to simultaneously consider the three constraints for analog routing while minimizing total wirelength, bend numbers, via counts, and coupling noise at the same time. We first present an integer linear programming (ILP) formulation to simultaneously consider the three constraints for analog routing, and employ effective reduction techniques to further reduce the numbers of ILP variables and constraints. Then, a non-uniform multilevel routing framework is presented to enhance the performance of our routing algorithm. Experimental results show that our approach can obtain better routing results and satisfy all specified routing constraints while optimizing circuit performance.