Efficient analog layout prototyping by layout reuse with routing preservation

Authors:
Ching-Yu Chin;Po-Cheng Pan;Hung-Ming Chen;Tung-Chieh Chen;Jou-Chun Lin
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;Synopsys Co., Ltd., Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2013

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Abstract

To strive for better circuit performance on analog design, layout generation heavily relies on experienced analog designers' effort. Other than general analog constraints such as symmetry and wire-matching are commonly embraced in many proposed works, analog circuit performance is also sensitive to routing behavior. This paper presents a CDT-based layout extraction to preserve routing behavior of the reference layout. Furthermore, a generalized layout prototyping methodology is proposed based on the layout extraction to achieve routing reuse. The proposed layout prototyping is applied to a variable-gain amplifier and a folded-cascode operational amplifier for both migration and prototypes generation. Experimental results show that our approach effectively reduces design cycle time and simultaneously produces reasonable performance.