Performance-driven analog placement considering monotonic current paths

Authors:
Po-Hsun Wu;Mark Po-Hung Lin;Yang-Ru Chen;Bing-Shiun Chou;Tung-Chieh Chen;Tsung-Yi Ho;Bin-Da Liu
Affiliations:
National Cheng Kung University, Tainan, Taiwan;National Chung Cheng University, Chiayi, Taiwan;National Cheng Kung University, Tainan, Taiwan;National Cheng Kung University, Tainan, Taiwan;SpringSoft, Inc., Hsinchu, Taiwan;National Cheng Kung University, Tainan, Taiwan;National Cheng Kung University, Tainan, Taiwan
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2012

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Abstract

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.