Optimal orientations of cells in slicing floorplan designs
Information and Control
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Fast floorplanning for effective prediction and construction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modern floorplanning based on B*-tree and fast simulated annealing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast floorplanning by look-ahead enabled recursive bipartitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast analog layout prototyping for nanometer design migration
Proceedings of the International Conference on Computer-Aided Design
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture
Proceedings of the International Conference on Computer-Aided Design
Performance-driven analog placement considering monotonic current paths
Proceedings of the International Conference on Computer-Aided Design
Line search-based inverse lithography technique for mask design
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
VLSI floorplanning based on the integration of adaptive search models
Journal of Computer and Systems Sciences International
LASER: layout-aware analog synthesis environment on laker
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Variable-Order Ant System for VLSI multiobjective floorplanning
Applied Soft Computing
Fast fixed-outline 3-D IC floorplanning with TSV co-placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient analog layout prototyping by layout reuse with routing preservation
Proceedings of the International Conference on Computer-Aided Design
Regularity-constrained floorplanning for multi-core processors
Integration, the VLSI Journal
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In this paper, we present DeFer--a fast, high-quality, scalable, and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a nonslicing floorplan by compacting a slicing floorplan. To find a good slicing floorplan, instead of searching through numerous slicing trees by simulated annealing as in traditional approaches, DeFer considers only one single slicing tree. However, we generalize the notion of slicing tree based on the principle of deferred decision making (DDM). When two subfloorplans are combined at each node of the generalized slicing tree, DeFer does not specify their orientations, the left-right/top-bottom order between them, and the slice line direction. DeFer even does not specify the slicing tree structure for small subfloorplan. In other words, we are deferring the decisions on these factors, which are specified arbitrarily at an early step in traditional approaches. Because of DDM, one slicing tree actually corresponds to a large number of slicing floorplan solutions, all of which are efficiently maintained in one single shape curve. With the final shape curve, it is straightforward to choose a good floorplan fitting into the fixed outline. Several techniques are also proposed to further optimize the wirelength. For both fixed-outline and classical floorplanning problems, experimental results show that DeFer achieves the best success rate, the best wirelength, the best runtime, and the best area on average compared with all other state-of-the-art floorplanners.