Optimal orientations of cells in slicing floorplan designs
Information and Control
An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Slicing floorplans with pre-placed modules
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Fast floorplanning for effective prediction and construction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
A wire length estimation technique utilizing neighborhood density equations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As the size and complexity of VLSI circuits increase, the needfor faster floorplanning algorithms also grows.In this work weintroduce Traffic, a new method for creating wire- and area-optimizedfloorplans.Through the use of connectivity groupling,simple geometry, and efficient data structures, Traffic achieveshigher result quality than Simulated Annealing (SA) in afraction of the time.This speed allows designers to explore alarge circuit design space in a reasonable amount of time,rapidly evaluate small changes to big circuits, and quicklyproduce initial solutions for other floorplanning algorithms.