Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Fast floorplanning for effective prediction and construction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DAC '82 Proceedings of the 19th Design Automation Conference
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Module packing based on the BSG-structure and IC layout applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
mPL6: a robust multilevel mixed-size placement engine
Proceedings of the 2005 international symposium on Physical design
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Robust mixed-size placement under tight white-space constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Constraint-driven floorplan repair
Proceedings of the 43rd annual Design Automation Conference
Floorplan repair using dynamic whitespace management
Proceedings of the 17th ACM Great Lakes symposium on VLSI
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
Constraint-driven floorplan repair
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving modern mixed-size placement instances
Integration, the VLSI Journal
Constraint graph-based macro placement for modern mixed-size circuit designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An effective approach for large scale floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Floorplanning considering IR drop in multiple supply voltages island designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post-hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time.