An O-tree representation of non-slicing floorplan and its applications

An enhanced perturbing algorithm for floorplan design using the O-tree representation

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Classical floorplanning harmful?

ISPD '00 Proceedings of the 2000 international symposium on Physical design

B*-Trees: a new representation for non-slicing floorplans

Proceedings of the 37th Annual Design Automation Conference

Block placement with symmetry constraints based on the O-tree non-slicing representation

Proceedings of the 37th Annual Design Automation Conference

Slicing tree is a complete floorplan representation

Proceedings of the conference on Design, automation and test in Europe

Automatic datapath tile placement and routing

Proceedings of the conference on Design, automation and test in Europe

Faster and more accurate wiring evaluation in interconnect-centric floorplanning

GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI

Slicing floorplan design with boundary-constrained modules

Proceedings of the 2001 international symposium on Physical design

Revisiting floorplan representations

Proceedings of the 2001 international symposium on Physical design

Consistent floorplanning with super hierarchical constraints

Proceedings of the 2001 international symposium on Physical design

ECBL: an extended corner block list with solution space including optimum placement

Proceedings of the 2001 international symposium on Physical design

Rectilinear block packing using O-tree representation

Proceedings of the 2001 international symposium on Physical design

Device-level placement for analog layout: an opportunity for non-slicing topological representations

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Slicing floorplan with clustering constraints

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

VLSI floorplanning with boundary constraints based on corner block list

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Module placement with boundary constraints using the sequence-pair representation

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

FAST-SP: a fast algorithm for block placement based on sequence pair

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Integrated power supply planning and floorplanning

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

VLSI block placement using less flexibility first principles

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

TCG: a transitive closure graph-based representation for non-slicing floorplans

Proceedings of the 38th annual Design Automation Conference

Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list

Proceedings of the 38th annual Design Automation Conference

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs

Proceedings of the 2002 international symposium on Physical design

Twin binary sequences: a non-redundant representation for general non-slicing floorplan

Proceedings of the 2002 international symposium on Physical design

TCG-S: orthogonal coupling of P*-admissible representations for general floorplans

Proceedings of the 39th annual Design Automation Conference

Floorplanning with alignment and performance constraints

Proceedings of the 39th annual Design Automation Conference

A polynomial-time optimization algorithm for a rectilinear partitioning problem with applications in VLSI design automation

Information Processing Letters

Corner block list: an effective and efficient topological representation of non-slicing floorplan

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Modeling non-slicing floorplans with binary trees

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Local search for final placement in VLSI design

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Floorplan representations: Complexity and connections

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Rectilinear block placement using B*-trees

ACM Transactions on Design Automation of Electronic Systems (TODAES)

An optimum placement search algorithm based on extended corner block list

Journal of Computer Science and Technology

Efficient solution space exploration based on segment trees in analog placement with symmetry constraints

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Multilevel floorplanning/placement for large-scale modules using B*-trees

Proceedings of the 40th annual Design Automation Conference

Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

Rectilinear Block Placement Using B*-Trees

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Corner sequence: a P-admissible floorplan representation with a worst case linear-time packing scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Deterministic VLSI block placement algorithm using less flexibility first principle

Journal of Computer Science and Technology

Floorplanning for throughput

Proceedings of the 2004 international symposium on Physical design

An area-optimality study of floorplanning

Proceedings of the 2004 international symposium on Physical design

Innovate or perish: FPGA physical design

Proceedings of the 2004 international symposium on Physical design

Practical slicing and non-slicing block-packing without simulated annealing

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Stairway compaction using corner block list and its applications with rectilinear blocks

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation

Proceedings of the 41st annual Design Automation Conference

A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Multi-Million Gate FPGA Physical Design Challenges

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Abstraction and optimization of consistent floorplanning with pillar block constraints

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Space-planning: placement of modules with controlled empty area by single-sequence

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

On handling arbitrary rectilinear shape constraint

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Thermal-Aware Floorplanning Using Genetic Algorithms

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Modern floorplanning based on fast simulated annealing

Proceedings of the 2005 international symposium on Physical design

Are floorplan representations important in digital design?

Proceedings of the 2005 international symposium on Physical design

Fast evaluation of bounded slice-line grid

Journal of Computer Science and Technology

Temporal floorplanning using the T-tree formulation

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

A thermal-driven floorplanning algorithm for 3D ICs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Simultaneous block and I/O buffer floorplanning for flip-chip design

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

A fixed-die floorplanning algorithm using an analytical approach

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Using red-black interval trees in device-level analog placement with symmetry constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

An improved P-admissible floorplan representation based on Corner Block List

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Fast floorplanning by look-ahead enabled recursive bipartitioning

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

LFF algorithm for heterogeneous FPGA floorplanning

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Placement with symmetry constraints for analog layout design using TCG-S

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Optimal redistribution of white space for wire length minimization

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Interconnect estimation without packing via ACG floorplans

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

SoC test scheduling using the B-tree based floorplanning technique

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Floorplan and power/ground network co-synthesis for fast design convergence

Proceedings of the 2006 international symposium on Physical design

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Module placement for fault-tolerant microfluidics-based biochips

Proceedings of the 41st annual Design Automation Conference

A stable fixed-outline floorplanning method

Proceedings of the 2007 international symposium on Physical design

A revisit to floorplan optimization by Lagrangian relaxation

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Fast wire length estimation by net bundling for block placement

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Analog placement with symmetry and other placement constraints

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

A new heuristic algorithm for rectangle packing

Computers and Operations Research

Power-density aware floorplanning for reducing maximum on-chip temperature

MOAS'07 Proceedings of the 18th conference on Proceedings of the 18th IASTED International Conference: modelling and simulation

Multi-bend bus driven floorplanning

Integration, the VLSI Journal

Effective decap insertion in area-array SoC floorplan design

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Exploring adjacency in floorplanning

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

T-trees: A tree-based representation for temporal and three-dimensional floorplanning

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A Parallel Simulated Annealing Approach for Floorplanning in VLSI

ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing

Handling complexities in modern large-scale mixed-size placement

Proceedings of the 46th Annual Design Automation Conference

Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Analog layout generator for CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Power-density aware floorplanning for reducing maximum on-chip temperature

MS '07 The 18th IASTED International Conference on Modelling and Simulation

A Discrete PSO for Multi-objective Optimization in VLSI Floorplanning

ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence

Genetic algorithms for VLSI micro-cell layout area optimization based on binary tree

ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology

Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Regularity-oriented analog placement with diffusion sharing and well island generation

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Configurable multi-product floorplanning

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

UFO: unified convex optimization algorithms for fixed-outline floorplanning

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Floorplanning for low power IC design considering temperature variations

Microelectronics Journal

Regularity-constrained floorplanning for multi-core processors

Proceedings of the 2011 international symposium on Physical design

TCG: a transitive closure graph-based representation for general floorplans

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm

ACM Transactions on Design Automation of Electronic Systems (TODAES)

On packing squares into a rectangle

Computational Geometry: Theory and Applications

An improved algorithm for sequence pair generation

ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I

A corner stitching compliant B*-tree representation and its applications to analog placement

Proceedings of the International Conference on Computer-Aided Design

Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip

Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

LAYGEN II: automatic analog ICs layout generator based on a template approach

Proceedings of the 14th annual conference on Genetic and evolutionary computation

Hierarchical congregated ant system for bottom-up VLSI placements

Engineering Applications of Artificial Intelligence

Multiple chip planning for chip-interposer codesign

Proceedings of the 50th Annual Design Automation Conference

Constraint-aware interior layout exploration for pre-cast concrete-based buildings

The Visual Computer: International Journal of Computer Graphics

Regularity-constrained floorplanning for multi-core processors

Integration, the VLSI Journal