An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Optimization of Dynamic Hardware Reconfigurations
The Journal of Supercomputing
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Temporal floorplanning using 3D-subTCG
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 42nd annual Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Module placement for fault-tolerant microfluidics-based biochips
Proceedings of the 41st annual Design Automation Conference
Placement of digital microfluidic biochips using the t-tree formulation
Proceedings of the 43rd annual Design Automation Conference
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
The minimization of hardware size in reconfigurable embedded platforms
Proceedings of the 2008 ACM symposium on Applied computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
From 3D circuit technologies and data structures to interconnect prediction
Proceedings of the 11th international workshop on System level interconnect prediction
Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
A tree based novel representation for 3D-block packing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Droplet-routing-aware module placement for cross-referencing biochips
Proceedings of the 19th international symposium on Physical design
Task Scheduling for Context Minimization in Dynamically Reconfigurable Platforms
Journal of Signal Processing Systems
Task scheduling for context minimization in dynamically reconfigurable platforms
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Floorplacement for partial reconfigurable FPGA-based systems
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
Investigating modern layout representations for improved 3d design automation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture-Aware reconfiguration-centric floorplanning for partial reconfiguration
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. We model each task as a 3D-box and deal with the temporal floorplanning/placement problem for dynamically reconfigurable FPGA architectures. We present a tree-based data structure, called T-trees, to represent the spatial and temporal relations among tasks. Each node in a T-tree has at most three children which represent the dimensional relationship among tasks. For the T-tree, we develop an efficient packing method and derive the condition to ensure the satisfaction of precedence constraints which model the temporal ordering among tasks induced by the execution of dynamically reconfigurable FPGAs. Experimental results show that our tree-based formulation can achieve significantly better solution quality with less execution time than the most recent state-of-the-art work.