Optimal FPGA module placement with temporal precedence constraints

  • Authors:
  • S. Fekete;E. Köhler;J. Teich

  • Affiliations:
  • Department of Mathematics, TU Berlin, Berlin, Germany;Department of Mathematics, TU Berlin, Berlin, Germany;Computer Engineering Laboratory, University of Paderborn, Paderborn, Germany

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2001

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Abstract