Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
RMB -- A Reconfigurable Multiple Bus Network
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Efficient symbolic multi-objective design space exploration
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Efficient Reconfigurable On-Chip Buses for FPGAs
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
FPGA: what's in it for a database?
Proceedings of the 2009 ACM SIGMOD International Conference on Management of data
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Proceedings of the Conference on Design, Automation and Test in Europe
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Self-organizing computer vision for robust object tracking in smart cameras
ATC'10 Proceedings of the 7th international conference on Autonomic and trusted computing
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Opt4J: a modular framework for meta-heuristic optimization
Proceedings of the 13th annual conference on Genetic and evolutionary computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design Optimizations for Tiled Partially Reconfigurable Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placing multimode streaming applications on dynamically partially reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Mapping on multi/many-core systems: survey of current and emerging trends
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
In today's complex embedded systems not all applications are running all the time, but depend on the operational mode. By incorporating knowledge about the temporal behavior of such multi-mode systems, it is possible to share hardware by means of partial reconfiguration, and thus, reduce costs and improve performance. In this paper, we specify the temporal behavior of the functionality by applying known models based on state machines. In addition, we introduce an architectural model that allows to express the characteristics of nowadays partially reconfigurable architectures, focusing on FPGAs. We develop a symbolic encoding of this novel system specification, which allows to perform a unified system synthesis for allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The proposed encoding enables the use of sophisticated optimization techniques, coupling a SAT solver with a Multi-objective Evolutionary Algorithm. The proposed methodology is highly applicable for building multi-mode systems on advanced reconfigurable technology. We demonstrate this by experiments on test-cases from the image processing domain applying state-of-the-art technology. The results show the superiority of the presented approach in terms of run-time and quality of the found solutions compared to existing system synthesis approaches.