Communications of the ACM - Special section on computer architecture
Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Computer
Topological Properties of Hypercubes
IEEE Transactions on Computers
Rearrangeable circuit-switched hypercube architectures for routing permutations
Journal of Parallel and Distributed Computing
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Architecture and Implementation of Vulcan
Proceedings of the 8th International Symposium on Parallel Processing
Randomized routing on fat-tress
SFCS '85 Proceedings of the 26th Annual Symposium on Foundations of Computer Science
A reconfigurable multi-function computing cache architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
On Reconfiguring Cache for Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Placement of intermodule connections on partially reconfigurable devices
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Journal of VLSI Signal Processing Systems
Symbolic design space exploration for multi-mode reconfigurable systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Placing multimode streaming applications on dynamically partially reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Scheduling light-trails on WDM rings
Journal of Parallel and Distributed Computing
Hi-index | 0.00 |
The heart of a massively parallel computer is its interconnection network. In this article we present a reconfigurable multiple bus network to support circuit switching as means of communication between the processors of a multiprocessor machine. The main contribution of the paper is in demonstrating the simplicity of the routing hardware whilst still providing modularity and full utilization of the multiple bus system. A comparison with major interconnection networks is also presented.