RMB -- A Reconfigurable Multiple Bus Network
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Siamese-Twin: A Dynamically Fault-Tolerant Fat-Tree
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
A collision model for randomized routing in fat-tree networks
Journal of Parallel and Distributed Computing
Federated grid clusters using service address routed optical networks
Future Generation Computer Systems
Area-time tradeoffs for universal VLSI circuits
Theoretical Computer Science
Exploring pattern-aware routing in generalized fat tree networks
Proceedings of the 23rd international conference on Supercomputing
Bandwidth-optimal all-to-all exchanges in fat tree networks
Proceedings of the 27th international ACM conference on International conference on supercomputing
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Fat-trees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor λ = Ω(lg n lg lg n) on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(λ) with probability 1-O(1/n). The best previous bound was O(λ lg n) for the off-line problem where switch settings can be determined in advance. In a VLSI-like model where hardware cost is equated with physical volume, we use the routing algorithm to demonstrate that fat-trees are universal routing networks in the sense that any routing network can be efficiently simulated by a fat-tree of comparable hardware cost.