Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Efficient simulations among several models of parallel computers
SIAM Journal on Computing
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
The network architecture of the Connection Machine CM-5 (extended abstract)
SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
An area-universal VLSI circuit
Proceedings of the 1993 symposium on Research on integrated systems
Randomized routing and sorting on fixed-connection networks
Journal of Algorithms
A lower bound for area-universal graphs
Information Processing Letters
The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay
IEEE Transactions on Computers
Deterministic on-line routing on area-universal networks
Journal of the ACM (JACM)
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
An Area Lower Bound for a Class of Fat-Trees (Extended Abstract)
ESA '94 Proceedings of the Second Annual European Symposium on Algorithms
A complexity theory for VLSI
Randomized routing on fat-tress
SFCS '85 Proceedings of the 26th Annual Symposium on Foundations of Computer Science
Universal emulations with sublogarithmic slowdown
SFCS '93 Proceedings of the 1993 IEEE 34th Annual Foundations of Computer Science
| Hi-index | 5.23 |
An area-universal VLSI circuit can be programmed to emulate every circuit of a given area, but at the cost of lower area-time performance. In particular, if a circuit with area-time bounds (A,T) is emulated by a universal circuit with bounds (A"u,T"u), we say that the universal circuit has blowup A"u/A and slowdown T"u/T. A central question in VLSI theory is to investigate the inherent costs and tradeoffs of universal circuit designs. Prior to this work, universal designs were known for area-A circuits with O(1) blowup and O(logA) slowdown. Universal designs for the family of area-A circuits containing O(A^1^+^@elogA) vertices, with O(A^@e) blowup and O(loglogA) slowdown had also been developed. However, the existence of universal circuits with O(1) slowdown and relatively small blowup was an open question. In this paper, we settle this question by designing an area-universal circuit U"A^^^@e with O(1/@e) slowdown and O(A^@e) blowup, for any value of the parameter @e, with 4loglogA/logA@?@e@?1. By varying @e, we obtain universal circuits which operate at different points in the spectrum of the slowdown-blowup tradeoff. In particular, when @e is chosen to be a constant, our universal circuit yields O(1) slowdown.