Efficient Schemes for Parallel Communication
Journal of the ACM (JACM)
Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
The generalized packet routing problem
Theoretical Computer Science
Sorting in c log n parallel steps
Combinatorica
Tight bounds on the complexity of parallel sorting
IEEE Transactions on Computers
A minimum area VLSI network for O(log n) time sorting
IEEE Transactions on Computers
Efficient dispersal of information for security, load balancing, and fault tolerance
Journal of the ACM (JACM)
Size-time complexity of Boolean networks for prefix computations
Journal of the ACM (JACM)
The token distribution problem
SIAM Journal on Computing
An O(logN) deterministic packet routing scheme
STOC '89 Proceedings of the twenty-first annual ACM symposium on Theory of computing
The fat-pyramid: a robust network for parallel computation
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
A note on the token distribution problem
Information Processing Letters
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Cubesort: A parallel algorithm for sorting N data items with S-sorters
Journal of Algorithms
Deterministic Simulations of Prams on Bounded Degree Networks
SIAM Journal on Computing
Journal of the ACM (JACM)
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Universal schemes for parallel communication
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Randomized parallel communication (Preliminary Version)
PODC '82 Proceedings of the first ACM SIGACT-SIGOPS symposium on Principles of distributed computing
A complexity theory for VLSI
The area-time complexity of sorting (algorithms, computation, architecture, vlsi)
The area-time complexity of sorting (algorithms, computation, architecture, vlsi)
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
Area-Universal Circuits with Constant Slowdown
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Siamese-Twin: A Dynamically Fault-Tolerant Fat-Tree
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 01
The fat-stack and universal routing in interconnection networks
Journal of Parallel and Distributed Computing - Special issue: 18th International parallel and distributed processing symposium
Area-time tradeoffs for universal VLSI circuits
Theoretical Computer Science
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Two deterministic routing networks are presented: the pruned butterfly and the sorting fat-tree. Both networks are area-universal, that is, they can simulate any other routing network fitting in similar area with polylogarithmic slowdown. Previous area-universal networks were either for the off-line problem, where the message set to be routed is known in advance and substantial precomputation is permitted, or involved randomization, yielding results that hold only with high probability. The two networks introduced here are the first that are simultaneously deterministic and on-line, and they use two substantially different routing techniques. The performance of their routing algorithms depends on the difficulty of the problem instance, which is measured by a quantity &lgr; known as the load factor. The pruned butterfly runs in time O(&lgr;log2N), is the number of possible sources and destinations for messages and &lgr; is assumed to be polynomial in N. The sorting fat-tree algorithm runs in O(&lgr; log N + log2 N) time for a restricted class of message sets including partial permutations. Other results of this work include a “flexible” circuit that is area-time optimal across a range of different input sizes and an area-time lower bound for routers based on wire-length arguments.