An optimal sorting algorithm for mesh connected computers
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
Optimal VLSI circuits for sorting
Journal of the ACM (JACM)
A Gracefully Degradable VLSI System for Linear Programming
IEEE Transactions on Computers
Optimal VLSI Sorting with Reduced Number of Processors
IEEE Transactions on Computers
Optimal bounded-degree VLSI networks for sorting in a constant number of rounds
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Sorting with Linear Speedup on a Pipelined Hypercube
IEEE Transactions on Computers
A New Class of Optimal Bounded-Degree VLSI Sorting Networks
IEEE Transactions on Computers
Deterministic on-line routing on area-universal networks
Journal of the ACM (JACM)
A simple architecture for constant time sorting machines
ACM SIGARCH Computer Architecture News
Improved routing and sorting on multibutterflies
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
How to Sort N Items Using a Sorting Network of Fixed I/O Size
IEEE Transactions on Parallel and Distributed Systems
A Generalized Simultaneous Access Dictionary Machine
IEEE Transactions on Parallel and Distributed Systems
Arbitrary long digit integer sorter HW/SW co-design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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A generalization of a known class of parallel sorting algorithms is presented, together with a new interconnection to execute them. A VLSI implementation is also proposed, and its area-time performance is discussed. It is shown that an algorithm in the class is executable in O(log n) time by a chip occupying O(n2) area. The design is a typical instance of a ``hybrid architecture,'' resulting from the combination of well-known VLSI networks as the orthogonal trees and the cube-connected cycles; it also provably meets the AT2 = 驴(n2 log2 n) lower bound for sorters of n words of length (1 + 驴) log n (驴 ≫ 0).