The VLSI optimality of the AKS sorting network
Information Processing Letters
Aspects of information flow in VLSI circuits
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
Optimal VLSI circuits for sorting
Journal of the ACM (JACM)
Sorting in c log n parallel steps
Combinatorica
Tight bounds on the complexity of parallel sorting
IEEE Transactions on Computers
A minimum area VLSI network for O(log n) time sorting
IEEE Transactions on Computers
Parallel Sorting in Two-Dimensional VLSI Models of Computation
IEEE Transactions on Computers
Optimal bounded-degree VLSI networks for sorting in a constant number of rounds
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Bounds to Complexities of Networks for Sorting and for Switching
Journal of the ACM (JACM)
Routing BPS Permutations in VLSI
IPPS '92 Proceedings of the 6th International Parallel Processing Symposium
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
The area-time complexity of sorting (algorithms, computation, architecture, vlsi)
The area-time complexity of sorting (algorithms, computation, architecture, vlsi)
Computational Aspects of VLSI
Optimal VLSI Networks for Multidimensional Transforms
IEEE Transactions on Parallel and Distributed Systems
| Hi-index | 14.98 |
Minimum-area very large scale integration (VLSI) networks have been proposed for sorting N elements in O(log,N) time. However, most of such networks proposed have complex structures, and no explicit network construction is given in others. New designs of optimal VLSI sorters that combine rotate-sort with enumeration-sort to sort N numbers, each of length w (1+ in )logN bits (for any constant in