Simulation of large networks on smaller networks
Information and Control
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
Tight bounds on the complexity of parallel sorting
IEEE Transactions on Computers
Optimal VLSI architectures for multidimensional DFT
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
VLSI Architectures for Multidimensional Transforms
IEEE Transactions on Computers
A New Class of Optimal Bounded-Degree VLSI Sorting Networks
IEEE Transactions on Computers
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM
Routing BPS Permutations in VLSI
IPPS '92 Proceedings of the 6th International Parallel Processing Symposium
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Computational Aspects of VLSI
New area-time lower bounds for the multidimensional DFT
CATS 2011 Proceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 119
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This paper presents a new class of AT/sup 2/-optimal networks for computing themultidimensional discrete Fourier transform. Although optimal networks have beenproposed previously, the networks proposed in this paper are based on a newmethodology for mapping large K-shuffle networks, K/spl ges/2, onto smaller areanetworks that maintain the optimality of the DFT network. Such networks are used toperform the index-rotation operations needed by the multidimensional computation. Theresulting networks have simple regular layouts, and can be easily partitioned among several chips in order to reduce the number of input-output pins per chip.