Introduction to combinatorial theory
Introduction to combinatorial theory
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
Optimal VLSI architectures for multidimensional DFT
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Multi-dimensional systolic networks, for discrete fourier transform
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Optimal VLSI Networks for Multidimensional Transforms
IEEE Transactions on Parallel and Distributed Systems
A systolic VLSI architecture for multi-dimensional transforms
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
New area-time lower bounds for the multidimensional DFT
CATS 2011 Proceedings of the Seventeenth Computing on The Australasian Theory Symposium - Volume 119
| Hi-index | 14.99 |
The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N*N* . . . *N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(N/sup d+2a/) and computation time T=O(dN/sup d/2-a/b), and achieve the AT/sup 2/ bound of AT/sup 2/=O(n/sup 2/b/sup 2/) for constant d, where n=N/sup d/ and Oaor=d/2.