VLSI array processors
VLSI Architectures for multidimensional fourier transform processing
IEEE Transactions on Computers
Synthesizing Linear Array Algorithms from Nested FOR Loop Algorithms
IEEE Transactions on Computers
Fundamentals of digital image processing
Fundamentals of digital image processing
Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
VLSI Architectures for Multidimensional Transforms
IEEE Transactions on Computers
Behavioral synthesis: digital system design using the synopsys behavioral compiler
Behavioral synthesis: digital system design using the synopsys behavioral compiler
DG2VHDL: A Tool to Facilitate the High Level Synthesisof Parallel Processing Array Architectures
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
VLSI Signal Processing Systems
VLSI Signal Processing Systems
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets
Multiresolution Signal Decomposition: Transforms, Subbands, and Wavelets
Multidimensional Digital Signal Processing
Multidimensional Digital Signal Processing
On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
Synchronizing large VLSI processor arrays
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Parallel architectures and algorithms for discrete wavelet transforms
Parallel architectures and algorithms for discrete wavelet transforms
Computational Aspects of VLSI
Low-power video encoder/decoder using wavelet/TSVQ with conditional replenishment
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
An efficient CORDIC array structure for the implementation ofdiscrete cosine transform
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method
IEEE Transactions on Circuits and Systems for Video Technology
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A framework for mapping systematically 2-dimensional (2-D) separable transforms into a parallel architecture consisting of fully pipelined linear array stages is presented. The resulting model architecture is characterized by its generality, high degree of modularity, high throughput, and the exclusive use of distributed memory and control. There is no central shared memory block to facilitate the transposition of intermediate results, as it is commonly the case in row-column image processing architectures. Avoiding shared central memory has positive implications for speed, area, power dissipation and scalability of the architecture. The architecture presented here may be used to realize any separable 2-D transform by only changing the coefficients stored in the processing elements. Pipelined linear arrays for computing the 2-D Discrete Fourier Transform and 2-D separable convolution are presented as examples and their performance is evaluated.