A Low Power 8 × 8 Direct 2-D DCT Chip Design
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
High Performance Array Processor for Video Decoding
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip
Journal of VLSI Signal Processing Systems
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
Microprocessors & Microsystems
Memory-efficient and high-performance 2-D DCT and IDCT processors based on CORDIC rotation
MUSP'07 Proceedings of the 7th WSEAS International Conference on Multimedia Systems & Signal Processing
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A parallel architecture for motion estimation and DCT computation in MPEG-2 encoder
ICA3PP'07 Proceedings of the 7th international conference on Algorithms and architectures for parallel processing
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
A high performance video transform engine by using space-time scheduling strategy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Among the various transform techniques for image compression, the discrete cosine transform (DCT) is the most popular and effective one in practical image and video coding applications, such as high-definition television (HDTV). We develop a novel 8×8 two-dimensional (2-D) discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture based on the direct 2-D approach and the rotation technique. The computational complexity is reduced by taking advantage of the special attribute of a complex number. Both the parallel and the folded architectures are proposed. Unlike other approaches, the proposed architecture is regular and economically allowable for VLSI implementation. Compared to the row-column method, less internal wordlength is needed in order to meet the error requirement of IDCT, and the throughput of the proposed architecture can achieve two times that of the row-column method with 30% hardware increased