Video Processing and Communications
Video Processing and Communications
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression
Proceedings of the 14th symposium on Integrated circuits and systems design
Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Shift-register-based data transposition for cost-effective discrete cosine transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 2.4-GS/s FFT processor for OFDM-based WPAN applications
IEEE Transactions on Circuits and Systems II: Express Briefs
High throughput DA-based DCT with high accuracy error-compensated adder tree
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient VLSI architectures for fast computation of the discreteFourier transform and its inverse
IEEE Transactions on Signal Processing
Fast algorithms for the discrete cosine transform
IEEE Transactions on Signal Processing
NEDA: a low-power high-performance DCT architecture
IEEE Transactions on Signal Processing
A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method
IEEE Transactions on Circuits and Systems for Video Technology
An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization
IEEE Transactions on Circuits and Systems for Video Technology
A new time distributed DCT architecture for MPEG-4 hardware reference model
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper, a spatial and time scheduling strategy, called the space-time scheduling (STS) strategy, that achieves high image resolutions in real-time systems is proposed. The proposed spatial scheduling strategy includes the ability to choose the distributed arithmetic (DA)-precision bit length, a hardware sharing architecture that reduces the hardware cost, and the proposed time scheduling strategy arranges different dimensional computations in that it can calculate first-dimensional and second-dimensional transformations simultaneously in single 1-D discrete cosine transform (DCT) core to reach a hardware utilization of 100%. The DA-precision bit length is chosen as 9 bits instead of the traditional 12 bits based on test image simulations. In addition, the proposed hardware sharing architecture employs a binary signed-digit DA architecture that enables the arithmetic resources to be shared during the four time slots. For this reason, the proposed 2-D DCT core achieves high accuracy with a small area and a high throughput rate and is verified using a TSMC 0.18-µm 1P6M CMOS process chip implementation. Measurement results show that the core has a latency of 84 clock cycles with a 52 dB peak-signal-to-noise-ratio and is operated at 167 MHz with 15.8 K gate counts.