Proceedings of the conference on Design, automation and test in Europe - Volume 3
When reconfigurable architecture meets network-on-chip
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Journal of VLSI Signal Processing Systems
RoSA: a reconfigurable stream-based architecture
Proceedings of the 20th annual conference on Integrated circuits and systems design
Experimental analysis of sequence dependence on energy saving for error tolerant image processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
A high performance video transform engine by using space-time scheduling strategy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Loop acceleration exploration for ASIP architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications
Multimedia Tools and Applications
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Abstract: This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two 1-D DCT calculations by using a transpose buffer. These parts are described in this paper, with an architectural discussion and the VHDL synthesis results as well. The 2-D DCT architecture uses 4,792 logic cells of one Altera Flex10kE FPGA and reaches an operating frequency of 12.2 MHz. One input block with 8 x 8 elements of 8 bits each is processed in 25.2µs and the pipeline latency is 160 clock cycles.