System level design with spade: an M-JPEG case study
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Trace driven modeling: Review and overview
ANSS '73 Proceedings of the 1st symposium on Simulation of computer systems
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression
Proceedings of the 14th symposium on Integrated circuits and systems design
A timing-accurate HW/SW co-simulation of an ISS with SystemC
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Calibration of abstract performance models for system-level design space exploration
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Performance evaluation at system level has become a prerequisite in the design process of modern System-on-Chip (SoC) architectures. This fact resulted in many simulative methods proposed by the research community. In trace-based simulations, the performance of SoC architectures is evaluated using abstracted traces. This paper presents an approach for the generation of the traces at the instruction level from a target SW code executed on a cycle accurate CPU simulator. We showed that the use of fine-grained traces provides accuracy above 95% with an increase of simulation performance by factor of 1.3 to 3.8 compared to the reference cycle accurate simulator. The resulting traces are used during high-level explorations in our trace-driven SystemC TLM simulator, in which performance of MPSoC (Multiprocessor SoC) architectures with a variable number of CPUs, diverse memory hierarchies and on-chip interconnect can be evaluated.