A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Combining simulation and formal methods for system-level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Formal performance analysis and simulation of UML/SysML models for ESL design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Probabilistic performance risk analysis at system-level
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Abstract, Multifaceted Modeling of Embedded Processors for System Level Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Software Performance Estimation in MPSoC Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Using a dataflow abstracted virtual prototype for HdS-design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-Level System Modeling for Rapid HW/SW Architecture Exploration
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
ESL power analysis of embedded processors for temperature and reliability estimations
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
TotalProf: a fast and accurate retargetable source code profiler
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Bottom-up performance analysis considering time slice based software scheduling at system level
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
An efficient approach for system-level timing simulation of compiler-optimized embedded software
Proceedings of the 46th Annual Design Automation Conference
Trace-driven workload simulation method for Multiprocessor System-On-Chips
Proceedings of the 46th Annual Design Automation Conference
Fast instruction cache modeling for approximate timed HW/SW co-simulation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Software performance simulation strategies for high-level embedded system design
Performance Evaluation
INFOCOM'10 Proceedings of the 29th conference on Information communications
TLM+ modeling of embedded HW/SW systems
Proceedings of the Conference on Design, Automation and Test in Europe
Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
White box performance analysis considering static non-preemptive software scheduling
Proceedings of the Conference on Design, Automation and Test in Europe
Source-level timing annotation for fast and accurate TLM computation model generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Platform modeling for exploration and synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast and accurate source-level simulation of software timing considering complex code optimizations
Proceedings of the 48th Design Automation Conference
Dominator homomorphism based code matching for source-level simulation of embedded software
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Extended SystemC Framework for Efficient HW/SW Co-Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Synchronization for hybrid MPSoC full-system simulation
Proceedings of the 49th Annual Design Automation Conference
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
Proceedings of the 49th Annual Design Automation Conference
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A distributed timing synchronization technique for parallel multi-core instruction-set simulation
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
On confident task-accurate performance estimation
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Combined WCET analysis of bitcode and machine code using control-flow relation graphs
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Fast and accurate cache modeling in source-level simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
Fast cache simulation for host-compiled simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
On robust task-accurate performance estimation
Proceedings of the 50th Annual Design Automation Conference
Accurately timed transaction level models for virtual prototyping at high abstraction level
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hybrid source-level simulation of data caches using abstract cache models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Accurate source-level simulation of embedded software with respect to compiler optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
IEEE/ACM Transactions on Networking (TON)
Automated, retargetable back-annotation for host compiled performance and power modeling
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents an approach for cycle-accurate simulation of embedded software by integration in an abstract SystemC model. Compared to existing simulation-based approaches, we present a hybrid method that resolves performance issues by combining the advantages of simulation-based and analytical approaches. In a first step, cycle-accurate static execution time analysis is applied at each basic block of a cross-compiled binary program using static processor models. After that, the determined timing information is back-annotated into SystemC for fast simulation of all effects that can not be resolved statically. This allows the consideration of data dependencies during run-time and the incorporation of branch prediction and cache models by efficient source code instrumentation. The major benefit of our approach is that the generated code can be executed very efficiently on the simulation host with approximately 90% of the speed of the untimed software without any code instrumentation.