The Unified Modeling Language user guide
The Unified Modeling Language user guide
System Design with SystemC
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Virtual prototyping of embedded platforms for wireless and multimedia
Proceedings of the conference on Design, automation and test in Europe: Proceedings
FPGA architecture characterization for system level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Timing simulation of interconnected AUTOSAR software-components
Proceedings of the conference on Design, automation and test in Europe
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Multi-granularity sampling for simulating concurrent heterogeneous applications
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Highly-cited ideas in system codesign and synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Model Transformations for the Compilation of Multi-processor Systems-on-Chip
Generative and Transformational Techniques in Software Engineering II
A mixed-level virtual prototyping environment for SystemC-based design methodology
Microelectronics Journal
Monotonicity and run-time scheduling
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
A high-level virtual platform for early MPSoC software development
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Bottom-up performance analysis considering time slice based software scheduling at system level
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System level simulation of autonomic SoCs with TAPES
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
White box performance analysis considering static non-preemptive software scheduling
Proceedings of the Conference on Design, Automation and Test in Europe
Test exploration and validation using transaction level models
Proceedings of the Conference on Design, Automation and Test in Europe
TLM automation for multi-core design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Fast and accurate source-level simulation of software timing considering complex code optimizations
Proceedings of the 48th Design Automation Conference
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
Accurately timed transaction level models for virtual prototyping at high abstraction level
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Transaction-level models (TLMs) address the problems of designing increasingly complex systems by raising the level of design abstraction above RTL. However, TLM terminology is presently a subject of contentious debate and a coherent set of TLM use-models have not been proposed. In this paper we propose a variety of TLM use-models that reveal paths through the TLM abstraction levels for various types of system. We begin by stating the abstraction levels that comprise 'transaction-level' and identify roles and responsibilities that apply within the use-models. We then take each use-model and discuss the type of system it applies to, the TLM abstraction levels it supports, and the design activites applied at those levels. We also consider the distribution of modeling effort between the various design rôles and apply that to descriptions of various use-model design flows.