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System Design with SystemC
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
System-level design: orthogonalization of concerns and platform-based design
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System design for DSP applications in transaction level modeling paradigm
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Heterogeneous MP-SoC: the solution to energy-efficient signal processing
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Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Systematic Transaction Level Modeling of Embedded Systems with SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
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System level power and performance modeling of GALS point-to-point communication interfaces
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
The design of a smart imaging core for automotive and consumer applications: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A SystemC Refinement Methodology for Embedded Software
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Combining simulation and formal methods for system-level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Scheduling refinement in abstract RTOS models
ACM Transactions on Embedded Computing Systems (TECS)
TLM/network design space exploration for networked embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Automatic generation of transaction level models for rapid design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Journal of Systems Architecture: the EUROMICRO Journal
CATS: cycle accurate transaction-driven simulation with multiple processor simulators
Proceedings of the conference on Design, automation and test in Europe
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IEEE Design & Test
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Shared resource access attributes for high-level contention models
Proceedings of the 44th annual Design Automation Conference
Event-based re-training of statistical contention models for heterogeneous multiprocessors
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
System-platforms-based SystemC TLM design of image processing chains for embedded applications
EURASIP Journal on Embedded Systems
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Calibration of abstract performance models for system-level design space exploration
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Graph based test case generation for TLM functional verification
Microprocessors & Microsystems
Integrating RTL IPs into TLM designs through automatic transactor generation
Proceedings of the conference on Design, automation and test in Europe
Slack analysis in the system design loop
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
ACM Transactions on Embedded Computing Systems (TECS)
MC-Sim: an efficient simulation tool for MPSoC designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
System level hardware design and simulation with SystemAda
ACM SIGAda Ada Letters
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Journal of Signal Processing Systems
on the design of a formal debugger for system architecture
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
A cycle-accurate transaction level SystemC model for a serial communication bus
Computers and Electrical Engineering
SystemAda: an ada based system-level hardware description language
ACM SIGAda Ada Letters
A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Proceedings of the 46th Annual Design Automation Conference
Assertion-based performance analysis for OCP systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System/network design-space exploration based on TLM for networked embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Reactivity in systemC transaction-level models
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
System level simulation of autonomic SoCs with TAPES
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
Fast and accurate protocol specific bus modeling using TLM 2.0
Proceedings of the Conference on Design, Automation and Test in Europe
Combined system synthesis and communication architecture exploration for MPSoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Towards a synthesis semantics for systemC channels
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Journal of Systems Architecture: the EUROMICRO Journal
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A flexible hybrid simulation platform targeting multiple configurable processors SoC
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
TLM automation for multi-core design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Platform modeling for exploration and synthesis
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Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Logical time: specification vs. implementation
ACM SIGSOFT Software Engineering Notes
Idea: simulation based security requirement verification for transaction level models
ESSoS'11 Proceedings of the Third international conference on Engineering secure software and systems
A fast and effective dynamic trace-based method for analyzing architectural performance
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Simulation-based equivalence checking between SystemC models at different levels of abstraction
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Computers and Electrical Engineering
High confidence embedded software design: a quadrotor helicopter case study
ACM SIGBED Review - Work-in-Progress (WiP) Session of the 2nd International Conference on Cyber Physical Systems
Leveraging reconfigurability in the hardware/software codesign process
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
GALS-Designer: A design framework for GALS software systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EPIDETOX: an ESL platform for integrated circuit design and tool exploration
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Specification and encoding of transaction interaction properties
Formal Methods in System Design
TwinsNet: a cooperative MIMO mobile sensor network
UIC'06 Proceedings of the Third international conference on Ubiquitous Intelligence and Computing
Standards for system level design
Proceedings of the International Conference on Computer-Aided Design
Implementing OS components in hardware using AOP
ACM SIGOPS Operating Systems Review
A case for visualization-integrated system-level design space exploration
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Exploring design space using transaction level models
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
A fast MPSoC virtual prototyping for intensive signal processing applications
Microprocessors & Microsystems
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Synthesis of optimized hardware transactors from abstract communication specifications
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
From RTL IP to functional system-level models with extra-functional properties
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On the Reuse of TLM Mutation Analysis at RTL
Journal of Electronic Testing: Theory and Applications
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
A systematic approach to configurable functional verification of HW IP blocks at transaction level
Computers and Electrical Engineering
Completeness-driven development
ICGT'12 Proceedings of the 6th international conference on Graph Transformations
Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking
Proceedings of the Conference on Design, Automation and Test in Europe
Automated construction of a cycle-approximate transaction level model of a memory controller
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Evaluation of a new RFID system performance monitoring approach
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 8th ACM workshop on Performance monitoring and measurement of heterogeneous wireless and wired networks
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Microprocessors & Microsystems
Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms
Diagnosing root causes of system level performance violations
Proceedings of the International Conference on Computer-Aided Design
Automatic Generation of System Level Assertions from Transaction Level Models
Journal of Electronic Testing: Theory and Applications
A Novel Formalism for Partially Defined Asynchronous Feedback Digital Circuits
Journal of Electronic Testing: Theory and Applications
Full Length Article: Aspect-oriented RTL HW design using SystemC
Microprocessors & Microsystems
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Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models(TLMs) are not well defined and the usage of TLMs in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is not well coordinated. This paper introduces a TLM taxonomy and compares the benefits of TLMs' use.