System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The C++ Programming Language, Third Edition
The C++ Programming Language, Third Edition
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SystemC: From the Ground Up
A multi-model power estimation engine for accuracy optimization
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Activity-sensitive architectural power analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early power estimation for VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL-Aware Cycle-Accurate Functional Power Estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL IP to functional system-level models with extra-functional properties
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design of a low-energy data processing architecture for WSN nodes
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Microprocessors & Microsystems
| Hi-index | 0.00 |
Today's highly integrated System-on-Chips (SoC) demand innovative architectural modeling means to cope with their energy constraints. In this context, SystemC has become a well-established simulation tool for Transaction Level Modeling (TLM) in the integrated electronics industry but it lacks the support for power modeling. This paper introduces ActivaSC, a flexible, fast, transparent and non-intrusive extension to the SystemC class library which allows capturing the activity information of a digital system being modeled. This information can then be post-processed to estimate power consumption. ActivaSC avoids time consuming design iterations as designers can assess architectural design trade-offs based on system activity early in the design flow. ActivaSC does not require any code alterations nor a specific API, so that it can be used with any modeling style. Finally, several benchmark tests illustrate the superior efficiency of ActivaSC. A speed-up of up to 75% in terms of elaboration overhead and 20% in terms of simulation overhead is realized with respect to prior art.