Test strategies for low power devices
Proceedings of the conference on Design, automation and test in Europe
Functional Verification of Power Gated Designs by Compositional Reasoning
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Noise minimization during power-up stage for a multi-domain power network
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fault modeling and testing of retention flip-flops in low power designs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
NBTI-aware sleep transistor design for reliable power-gating
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Functional verification of power gate design in SystemC RTL
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Functional verification of power gated designs by compositional reasoning
Formal Methods in System Design
Proceedings of the 46th Annual Design Automation Conference
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A cost-effective load-balancing policy for tile-based, massive multi-core packet processors
ACM Transactions on Embedded Computing Systems (TECS)
Collaborative voltage scaling with online STA and variable-latency datapath
Proceedings of the 20th symposium on Great lakes symposium on VLSI
The challenges of implementing fine-grained power gating
Proceedings of the 20th symposium on Great lakes symposium on VLSI
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Hardware-based load balancing for massive multicore architectures implementing power gating
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Full passive UHF tag with a temperature sensor suitable for human body temperature monitoring
IEEE Transactions on Circuits and Systems II: Express Briefs
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-silicon is too late avoiding the $50 million paperweight starts with validated designs
Proceedings of the 47th Design Automation Conference
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Wakeup synthesis and its buffered tree construction for power gating circuit designs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Gate-sizing-based single Vdd test for bridge defects in multivoltage designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan based methodology for reliable state retention power gating designs
Proceedings of the Conference on Design, Automation and Test in Europe
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
Proceedings of the Conference on Design, Automation and Test in Europe
Selective state retention design using symbolic simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing energy to minimize errors in dataflow graphs using approximate adders
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Fast computation of discharge current upper bounds for clustered power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Residue arithmetic for designing low-power multiply-add units
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Design and optimization of power-gated circuits with autonomous data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Automated mapping for reconfigurable single-electron transistor arrays
Proceedings of the 48th Design Automation Conference
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
BSAA: a switching activity analysis and visualisation tool for soc power optimisation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A theory of abstraction for arrays
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
A hierarchical distributed control for power and performances optimization of embedded systems
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
An optimization mechanism intended for static power reduction using dual-Vth technique
Journal of Electrical and Computer Engineering
Regaining throughput using completion detection for error-resilient, near-threshold logic
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 27th Annual ACM Symposium on Applied Computing
Practically scalable floorplanning with voltage island generation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
An ARM perspective on addressing low-power energy-efficient SoC designs
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Static low power verification at transistor level for SoC design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Versatile design of shared vector coprocessors for multicores
Microprocessors & Microsystems
VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms
International Journal of Circuit Theory and Applications
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Efficient multiple-bit retention register assignment for power gated design: concept and algorithms
Proceedings of the International Conference on Computer-Aided Design
Open systemc simulator with support for power gating design
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Automated determination of top level control signals
Proceedings of the Conference on Design, Automation and Test in Europe
Power gating applied to MP-SoCs for standby-mode power management
Proceedings of the 50th Annual Design Automation Conference
Towards process variation-aware power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multicore-based vector coprocessor sharing for performance and energy gains
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Power optimization for clock network with clock gate cloning and flip-flop merging
Proceedings of the 2014 on International symposium on physical design
Leveraging rule-based designs for automatic power domain partitioning
Proceedings of the International Conference on Computer-Aided Design
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Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach. Richard Goering, Software Editor, EE Times Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion. Sujeeth Joseph, Chief Architect - Semiconductorand Systems Solutions Unit, Wipro Technologies The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs. Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc. Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management. Nick Salter, Head of Chip Integration, CSR plc.