New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM

Authors:
Ce Li;Yiping Dong;Takahiro Watanabe
Affiliations:
Waseda University, Kitakyushu, Japan;Waseda University, Kitakyushu, Japan;Waseda University, Kitakyushu, Japan
Venue:
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Year:
2011

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Abstract

The power consumption of FPGA is larger than that of ASIC to perform the same function in the same scaling. In this paper, we propose a Power Control Hard Macro (PCHM) based coarse-grained power gating FPGA architecture to dynamically reduce the power consumption. The algorithm of the placement based on sleep region is presented. After enhancing the CAD framework, a detailed study is given under different region size supported by the new FPGA architecture. As a result, the proposed architecture and the placement algorithm can reduce 51% power consumption on average compared with normal architecture.