Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploiting temporal idleness to reduce leakage power in programmable architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies (Springer Series in Advanced Microelectronics)
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Optimal MTCMOS reactivation under power supply noise and performance constraints
Proceedings of the conference on Design, automation and test in Europe
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
IR-drop management CAD techniques in FPGAs for power grid reliability
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
IR-Drop Aware Clustering Technique for Robust Power Grid in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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A dynamically-controlled power-gated (DCPG) FPGA architecture has recently been proposed to reduce static energy dissipation during idle periods. During a power mode transition from an off state to on state, the wakeup current drawn from power supplies causes a voltage droop on the power distribution network of a device. If not handled appropriately, this current and the associated voltage droop could cause malfunction of the design and/or the device. In DCPG FPGAs, the amount of wakeup current is not known beforehand as the structures of power-gated modules are application dependent; thus, a configurable solution is required to handle wakeup current. In this paper we propose a programmable wakeup architecture for DCPG FPGAs. The proposed solution has two levels: a fixed intra-region level and a configurable inter-region level. The architecture ensures that a power-gated module can be turned on such that the wakeup current constraints are not violated. We study the area and power overheads of the proposed solution. Our results show that the area overhead of the proposed inrush current limiting architecture is less than 2% for a power gating region of size 3x3 or 4x4 tiles, and the leakage power saved is more than 85% in a region of size 4x4 tiles.