Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Design tradeoffs for tiled CMP on-chip networks
Proceedings of the 20th annual international conference on Supercomputing
Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thermally robust clocking schemes for 3D integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Accurate temperature-dependent integrated circuit leakage power estimation is easy
Proceedings of the conference on Design, automation and test in Europe
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Proceedings of the conference on Design, automation and test in Europe
Skewed flip-flop transformation for minimizing leakage in sequential circuits
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Nanometer device scaling in subthreshold circuits
Proceedings of the 44th annual Design Automation Conference
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A low-power SRAM using bit-line charge-recycling technique
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
TORCH: a design tool for routing channel segmentation in FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Full-chip leakage current estimation based on statistical sampling techniques
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Signal Processing Systems
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A probabilistic technique for full-chip leakage estimation
Proceedings of the 13th international symposium on Low power electronics and design
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Guiding circuit level fault-tolerance design with statistical methods
Proceedings of the conference on Design, automation and test in Europe
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stack sizing for optimal current drivability in subthreshold in circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
UDSM subthreshold leakage model for NMOS transistor stacks
Microelectronics Journal
Breaking the simulation barrier: SRAM evaluation through norm minimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Thermal-aware reliability analysis for platform FPGAs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Manufacturability-Aware Design of Standard Cells
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An interconnect-aware delay model for dynamic voltage scaling in NM technologies
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analog Integrated Circuits and Signal Processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Compact non-binary fast adders using single-electron devices
Microelectronics Journal
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Proceedings of the 46th Annual Design Automation Conference
Variability analysis under layout pattern-dependent rapid-thermal annealing process
Proceedings of the 46th Annual Design Automation Conference
Design of thermally robust clock trees using dynamically adaptive clock buffers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
The BubbleWrap many-core: popping cores for sequential acceleration
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Mitigating the impact of variability on chip-multiprocessor power and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient FPGAs using nanoelectromechanical relays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Rapid design space exploration using legacy design data and technology scaling trend
Integration, the VLSI Journal
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Impact of shrinking technologies on the activation function of neurons
ICANN'07 Proceedings of the 17th international conference on Artificial neural networks
Low power nanoscale buffer management for network on chip routers
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Design and test strategies for microarchitectural post-fabrication tuning
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A technology-agnostic simulation environment (TASE) for iterative custom ic design across processes
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
Proceedings of the 37th annual international symposium on Computer architecture
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A new quaternary FPGA based on a voltage-mode multi-valued circuit
Proceedings of the Conference on Design, Automation and Test in Europe
A unified online fault detection scheme via checking of stability violation
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting clock skew scheduling for FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Low-leakage storage cells for ternary content addressable memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of single-electron tunneling transistors for designing low-power embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Repeater insertion in power-managed VLSI systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores
Proceedings of the 48th Design Automation Conference
A case for NEMS-based functional-unit power gating of low-power embedded microprocessors
Proceedings of the 48th Design Automation Conference
Enabling system-level modeling of variation-induced faults in networks-on-chips
Proceedings of the 48th Design Automation Conference
The route to a defect tolerant LUT through artificial evolution
Genetic Programming and Evolvable Machines
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
N3ASICs: Designing nanofabrics with fine-grained CMOS integration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
From Transistors to NEMS: Highly Efficient Power-Gating of CMOS Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning
Proceedings of the International Conference on Computer-Aided Design
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis
Proceedings of the International Conference on Computer-Aided Design
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A resistive TCAM accelerator for data-intensive computing
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
PARDIS: a programmable memory controller for the DDRx interfacing standards
Proceedings of the 39th Annual International Symposium on Computer Architecture
Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
Proceedings of the Conference on Design, Automation and Test in Europe
AC-DIMM: associative computing with STT-MRAM
Proceedings of the 40th Annual International Symposium on Computer Architecture
Reducing memory access latency with asymmetric DRAM bank organizations
Proceedings of the 40th Annual International Symposium on Computer Architecture
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation
Proceedings of the 50th Annual Design Automation Conference
Understanding the trade-offs in multi-level cell ReRAM memory design
Proceedings of the 50th Annual Design Automation Conference
Exploiting process variability in voltage/frequency control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Scalable high-radix router microarchitecture using a network switch organization
ACM Transactions on Architecture and Code Optimization (TACO)
A programmable memory controller for the DDRx interfacing standards
ACM Transactions on Computer Systems (TOCS)
DESC: energy-efficient data exchange using synchronized counters
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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Predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and physical correlations among model parameters, must be included. In addition, predictions across technology generations should be smooth to make continuous extrapolations. In this work, a new generation of Predictive Technology Model (PTM) is developed to accomplish these goals. Based on physical models and early stage silicon data, PTM of bulk CMOS for 130nm to 32nm technology nodes is successfully generated. By tuning ten parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified: for NMOS, the error of Ion is 2% and for PMOS, it is 5%. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. A webpage has been established for the release of PTM (http://www.eas.asu.edu/~ptm).