Design For Degradation: CAD Tools for Managing Transistor Degradation Mechanisms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NBTI-aware flip-flop characterization and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Bounded-lifetime integrated circuits
Proceedings of the 45th annual Design Automation Conference
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Using soft-edge flip-flops to compensate NBTI-induced delay degradation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NBTI-aware sleep transistor design for reliable power-gating
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Multi-mechanism reliability modeling and management in dynamic systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning
Proceedings of the 2009 International Conference on Computer-Aided Design
The Predictive Technology Model in the Late Silicon Era and Beyond
Foundations and Trends in Electronic Design Automation
Skew management of NBTI impacted gated clock trees
Proceedings of the 19th international symposium on Physical design
Aging effects of leakage optimizations for caches
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS
Proceedings of the 20th symposium on Great lakes symposium on VLSI
The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM-based NBTI/PBTI sensor system design
Proceedings of the 47th Design Automation Conference
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Investigating the impact of NBTI on different power saving cache strategies
Proceedings of the Conference on Design, Automation and Test in Europe
Programmable aging sensor for automotive safety-critical applications
Proceedings of the Conference on Design, Automation and Test in Europe
A resilience roadmap: (invited paper)
Proceedings of the Conference on Design, Automation and Test in Europe
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Minimization of NBTI performance degradation using internal node control
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and optimization of NBTI induced clock skew in gated clock trees
Proceedings of the Conference on Design, Automation and Test in Europe
Gate replacement techniques for simultaneous leakage and aging optimization
Proceedings of the Conference on Design, Automation and Test in Europe
A unified online fault detection scheme via checking of stability violation
Proceedings of the Conference on Design, Automation and Test in Europe
An on-chip NBTI sensor for measuring pMOS threshold voltage degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Controlling NBTI degradation during static burn-in testing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A linear programming approach for minimum NBTI vector selection
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Buffering of frequent accesses for reduced cache aging
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Integration, the VLSI Journal
Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage power and circuit aging cooptimization by gate replacement techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
In-field aging measurement and calibration for power-performance optimization
Proceedings of the 48th Design Automation Conference
Impact of NBTI on performance of domino logic circuits in nano-scale CMOS
Microelectronics Journal
Delay sensing for long-term variations and defects monitoring in safety---critical applications
Analog Integrated Circuits and Signal Processing
Failure diagnosis of asymmetric aging under NBTI
Proceedings of the International Conference on Computer-Aided Design
A self-evolving design methodology for power efficient multi-core systems
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
NBTI mitigation in microprocessor designs
Proceedings of the great lakes symposium on VLSI
Efficient selection and analysis of critical-reliability paths and gates
Proceedings of the great lakes symposium on VLSI
Physics matters: statistical aging prediction under trapping/detrapping
Proceedings of the 49th Annual Design Automation Conference
Identification of recovered ICs using fingerprints from a light-weight on-chip sensor
Proceedings of the 49th Annual Design Automation Conference
Static NBTI Reduction Using Internal Node Control
ACM Transactions on Design Automation of Electronic Systems (TODAES)
M-IVC: Applying multiple input vectors to co-optimize aging and leakage
Microelectronics Journal
A self-tuning design methodology for power-efficient multi-core systems
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A novel gate-level NBTI delay degradation model with stacking effect
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Reliability analysis reloaded: how will we survive?
Proceedings of the Conference on Design, Automation and Test in Europe
Impact of adaptive voltage scaling on aging-aware signoff
Proceedings of the Conference on Design, Automation and Test in Europe
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
Proceedings of the 50th Annual Design Automation Conference
Variation-aware supply voltage assignment for simultaneous power and aging optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact degradation sensors for monitoring NBTI and oxide degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Application-specific memory partitioning for joint energy and lifetime optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011
Critical-reliability path identification and delay analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the degradation of NBTI in both static and dynamic operations. Model scalability and generality are comprehensively verified with experimental data over a wide range of process and bias conditions. By implementing the new model into SPICE for an industrial 90nm technology, key insights are obtained for the development of robust design solutions: (1) the most effective techniques to mitigate the NBTI degradation are VDD tuning, PMOS sizing, and reducing the duty cycle; (2) an optimal VDD exists to minimize the degradation of circuit performance; (3) tuning gate length or the switching frequency has little impact on the NBTI effect; (4) a new switching scenario is identified for worst case timing analysis during NBTI stress.