A physical alpha-power law MOSFET model
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Minimizing stand-by leakage power in static CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Impact of Test Point Insertion on Silicon Area and Timing during Layout
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Combating NBTI Degradation via Gate Sizing
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Modeling of PMOS NBTI Effect Considering Temperature Variation
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
An efficient method to identify critical gates under circuit aging
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Penelope: The NBTI-Aware Processor
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
A linear programming formulation for security-aware gate sizing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimization of NBTI performance degradation using internal node control
Proceedings of the Conference on Design, Automation and Test in Europe
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates
Proceedings of the great lakes symposium on VLSI
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NBTI mitigation by optimized NOP assignment and insertion
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Transistor aging is a serious reliability challenge for nanoscale CMOS technology which can significantly reduce the operation lifetime of VLSI chips. Negative Bias Temperature Instability (NBTI) is the major contributor to transistor aging which affect PMOS transistors. The input vectors applied to the logic core has a significant impact on the overall aging of the logic block. In this paper, we present an efficient input vector selection technique based on Linear Programming (LP) to be used for maximum relaxation during the standby phase. We consider an accurate delay model for post-aging critical paths. Our mixed-LP (binary-relaxed) formulation scales well for very large circuits and provides near-optimal solutions. Experimental results and comparison with Monte-Carlo simulations show the speedup (4-5 orders of magnitude) and further optimization (11%) of our approach. Using these input vectors for the standby phase, the aging effect can be postponed by 71% in average.