Combating NBTI Degradation via Gate Sizing

Authors:
Xiangning Yang;Kewal Saluja
Affiliations:
University of Wisconsin-Madison, USA;University of Wisconsin-Madison, USA
Venue:
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Year:
2007

Citing 0
Cited 12

A linear programming formulation for security-aware gate sizing

Proceedings of the 18th ACM Great Lakes symposium on VLSI
NBTI resilient circuits using adaptive body biasing

Proceedings of the 18th ACM Great Lakes symposium on VLSI
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
SRAM-based NBTI/PBTI sensor system design

Proceedings of the 47th Design Automation Conference
Aging-resilient design of pipelined architectures using novel detection and correction circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Joint logic restructuring and pin reordering against NBTI-induced performance degradation

Proceedings of the Conference on Design, Automation and Test in Europe
NBTI-aware power gating design

Proceedings of the 16th Asia and South Pacific Design Automation Conference
A linear programming approach for minimum NBTI vector selection

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Buffering of frequent accesses for reduced cache aging

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits

Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates

Proceedings of the great lakes symposium on VLSI
Aging-aware logic synthesis

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

NBTI is becoming one of the dominant circuit reliability concerns in nano-scale technologies. We believe that designers can combat NBTI degradation using appropriate circuit constraints. This paper presents a design technique to tolerate NBTI degradation by gate sizing. We provide an NBTI-aware gate sizing problem formulation and propose a solution method. The experimental results for MCNC'91 benchmark circuits show that for NBTI tolerance the purposed method results in less than 1% area increase in most cases while a formulation based on traditional performance focused methods may lead to over 4% area increase.