Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Security in embedded systems: Design challenges
ACM Transactions on Embedded Computing Systems (TECS)
A New Statistical Optimization Algorithm for Gate Sizing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Computers
A novel approach for variation aware power minimization during gate sizing
Proceedings of the 2006 international symposium on Low power electronics and design
Combating NBTI Degradation via Gate Sizing
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A digital design flow for secure integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic security domain scaling on embedded symmetric multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
A linear programming approach for minimum NBTI vector selection
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Differential power analysis (DPA) has been shown to be the dominant type of side-channel attacks that significantly jeopardize the security in integrated circuits. It has been shown that the data, the functional unit operations as well as the internal micro-architectures can be detected through current and power analysis. Subsequently, different CMOS logic styles have been proposed in the literature for performing computations in such a manner that the current and power signatures can be concealed through reduction of the variance in transient power dissipation. In this work, we propose a gate sizing formulation based on traditional static CMOS standard cells that improves the security of the circuits while maintaining low overheads in terms of area, power and delay. The proposed algorithm considers all disjoint paths from primary inputs to the primary outputs, performing gate sizing with the objective of balancing the switched path capacitances among the various paths making it difficult to extract power or current signatures through current or power profiling. Further, we show that the path based security aware gate sizing formulation is NP-complete and propose a greedy approximation algorithm based on linear programming. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks and the experimental results indicate a reduction of the variance of transient dynamic power by about 40% with very low overhead in terms of delay, area and power.