Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Interconnect coupling noise in CMOS VLSI circuits
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Stackelberg scheduling strategies
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
Algorithms, games, and the internet
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
FOCS '02 Proceedings of the 43rd Symposium on Foundations of Computer Science
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Post-Route Gate Sizing for Crosstalk Noise Reduction
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multievent Crisis Management Using Noncooperative Multistep Games
IEEE Transactions on Computers
A linear programming formulation for security-aware gate sizing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power
Proceedings of the 13th international symposium on Low power electronics and design
Gate sizing for cell-library-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The continuous scaling trends of interconnect wires in deep submicron (DSM) circuits result in increased interconnect delay and crosstalk noise. In this work, we develop a new postlayout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. The problem of postlayout gate sizing is modeled as a normal form game and solved using Nash equilibrium. The crosstalk noise induced on a net depends on the size of its driver gate and the size of the gates driving its coupled nets. Increasing the gate size of the driver increases the noise induced by the net on its coupled nets, whereas increasing the size of the drivers of coupled nets increases the noise induced on the net itself, resulting in a cyclic order dependency leading to a conflicting situation. It is pointed out in [1] that solving the postroute gate sizing problem for crosstalk noise optimization is difficult due to its conflicting nature. Game theory provides a natural framework for handling such conflicting situations and allows optimization of multiple parameters. By utilizing this property of game theory, the cyclic dependency of crosstalk noise on its gate sizes can be solved as well as the problem of gate sizing for simultaneous optimization of interconnect delay and crosstalk noise can be effectively modeled, whose objective function is again conflicting in nature. We have implemented two different strategies in which games are ordered according to 1) the noise criticality and 2) delay criticality of nets. The time and space complexities of the proposed gate sizing algorithm are linear in terms of the number of gates in the design. Experimental results for a noise critically ordered game theoretic approach on several medium and large open core designs indicate average improvements of 15.48 percent and 18.56 percent with respect to Cadence place and route tools in terms of interconnect delay and crosstalk noise, respectively, without any area overhead or the need for rerouting. Further, the algorithm performs significantly better than simulated annealing and genetic search as established through experimental results. A mathematical proof of existence for the Nash equilibrium solution for the proposed gate sizing formulation is also provided.