Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Post-route gate sizing for crosstalk noise reduction
Proceedings of the 40th annual Design Automation Conference
Optimal gate sizing for coupling-noise reduction
Proceedings of the 2004 international symposium on Physical design
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
IEEE Transactions on Computers
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Single Event crosstalk shielding for CMOS logic
Microelectronics Journal
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: Digital circuits manufactured in deep sub-micron technologies may experience crosstalk-induced delay and noise signals. Crosstalk-induced delay can be quite significant and sensitive to the driver strength of coupling neighbors. In this paper, we propose gate-sizing techniques to reduce delay in presence of crosstalk effects. The techniques are based on our previously proposed crosstalk aware static timing analysis. Our experiments show that the proposed techniques are effective and may help designers achieve faster timing closure.