Stochastic versus possibilistic programming
Fuzzy Sets and Systems
Proceedings of the 37th Annual Design Automation Conference
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2003 international symposium on Low power electronics and design
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
A New Statistical Optimization Algorithm for Gate Sizing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Statistical Gate Sizing for Yield Enhancement at Post Layout Level
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Technology scaling has not only magnified the effects of device process variations, but it has also precipitated the need for simultaneous optimization of several performance metrics. In this paper, we propose a novel gate sizing approach for multi-metric optimization of delay, power, and crosstalk noise. The algorithm is based on the concepts of mathematical programming, and models the process variation uncertainty considering spatial correlations. The approach identifies leakage power, dynamic power, and crosstalk noise as the objectives, and the optimized gate delays are kept as constraints. Initially, the deterministic upper and lower bounds of the objectives are identified, and during the final step, a crisp non-linear programming problem is formulated using these boundary values. The problem is solved using KNITRO, an interior-point based optimization solver. The proposed model maximizes the variation resistance, thus providing higher yield. ITC'99 benchmarks were used to test the proposed approach, and the results indicate that our algorithm identifies the solution points that are closest to the nominal bounds, while maintaining high timing yield.