Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2004 international symposium on Low power electronics and design
Proceedings of the 42nd annual Design Automation Conference
CAD tools for variation tolerance
Proceedings of the 42nd annual Design Automation Conference
An Ultra Low Power System Architecture for Sensor Network Applications
Proceedings of the 32nd annual international symposium on Computer Architecture
Probabilistic dual-Vth leakage optimization under variability
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A Soft Error Monitor Using Switching Current Detection
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Modeling and estimation of full-chip leakage current considering within-die correlation
Proceedings of the 44th annual Design Automation Conference
Statistical analysis of full-chip leakage power considering junction tunneling leakage
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A probabilistic technique for full-chip leakage estimation
Proceedings of the 13th international symposium on Low power electronics and design
Multi-optimization power management for chip multiprocessors
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Stochastic thermal simulation considering spatial correlated within-die process variations
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Full-chip model for leakage-current estimation considering within-die correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Integration, the VLSI Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A linear statistical analysis for full-chip leakage power with spatial correlation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Accurate estimation of vector dependent leakage power in the presence of process variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
Full-chip leakage analysis for 65nm CMOS technology and beyond
Integration, the VLSI Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimation of FMAX and ISB in microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leak-Gauge: A late-mode variability-aware leakage power estimation framework
Microprocessors & Microsystems
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We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.