Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Managing multi-configuration hardware via dynamic working set analysis
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power Variability and Its Impact on Design
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Power efficiency for variation-tolerant multicore processors
Proceedings of the 2006 international symposium on Low power electronics and design
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Block remap with turnoff: a variation-tolerant cache design technique
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation
Proceedings of the 13th international symposium on Low power electronics and design
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Speed scaling with an arbitrary power function
SODA '09 Proceedings of the twentieth Annual ACM-SIAM Symposium on Discrete Algorithms
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Reducing leakage power with BTB access prediction
Integration, the VLSI Journal
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Process variation aware thread mapping for chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Variation-aware system-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM leakage reduction by row/column redundancy under random within-die delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transactions on high-performance embedded architectures and compilers III
Computers and Electrical Engineering
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Proceedings of the 49th Annual Design Automation Conference
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hardware/software approaches for reducing the process variation impact on instruction fetches
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Fine-grain voltage tuned cache architecture for yield management under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VaMV: variability-aware memory virtualization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a significant fraction of total power due to large on-chip caches, is exponentially dependent on widely varying physical parameters such as gate length, gate oxide thickness, and dopant ion concentration. In large structures like on-chip caches, this may mean that one portion of a cache may consume an order of magnitude larger static power than equivalently sized regions.Under this climate, egalitarian management of physical resources is clearly untenable. In this paper, we analyze the effects of within-die and die-to-die leakage variation for on-chip caches. We then propose way prioritization, a manufacturing variation aware scheme that minimizes cache leakage energy. Our results show that significant average power reductions are possible without undue hardware complexity or performance compromise.