Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Variations-aware low-power design with voltage scaling
Proceedings of the 42nd annual Design Automation Conference
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variation-aware voltage level selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The operational characteristics of integrated circuits in nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufacturing process and the operating environment. In this paper, we address the problem of incorporating the effects of variations into system-level power analysis tools. We consider both manufacturing-induced (die-to-die and within-die) variations in device characteristics, and operation-induced dynamic variations in on-chip temperature. To motivate our work, we first analyze the impact of variations on the power consumption of an example System-on-Chip (SoC). We show how simple extensions of current approaches to system-level power estimation (based on spreadsheets or system-level simulation) are not well-suited to performing variation-aware power-estimation. We propose a system-level power estimation methodology that accurately and efficiently analyzes the impact of variations on SoC power consumption. The proposed methodology combines fast trace analysis, power-state based leakage modeling, efficient thermal analysis, and Monte Carlo sampling to generate SoC power distributions, and power variability traces over time. The key benefit of the methodology is that it captures critical inter-dependencies between component workload profiles, leakage power, and variations in temperature and device parameters, while avoiding time-consuming iterative simulations. Our implementation of the proposed methodology within an in-house system-level power estimation framework indicates speedups of up to 4 orders of magnitude with negligible loss in accuracy as compared to Monte Carlo techniques. We also illustrate the application of our analysis framework can be used to explore a new class of "variation-aware" system-level power management techniques.