Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Statistically Aware SRAM Memory Array Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal Trends in Emerging Technologies
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
Proceedings of the 2006 international symposium on Low power electronics and design
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Architecting a reliable CMP switch architecture
ACM Transactions on Architecture and Code Optimization (TACO)
Prediction of leakage power under process uncertainties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The effect of process variation on device temperature in FinFET circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Full-chip leakage current estimation based on statistical sampling techniques
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A probabilistic technique for full-chip leakage estimation
Proceedings of the 13th international symposium on Low power electronics and design
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
System-level mitigation of WID leakage power variability using body-bias islands
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Measuring and modeling variabilityusing low-cost FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Proceedings of the 46th Annual Design Automation Conference
Variation-tolerant dynamic power management at the system-level
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware system-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Chip level statistical leakage power estimation using generalized extreme value distribution
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
A statistical model of logic gates for Monte Carlo simulation including on-chip variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware leakage power model extraction for system-level hierarchical power analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
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We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte-Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.