DAC '97 Proceedings of the 34th annual Design Automation Conference
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 40th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical estimation of leakage current considering inter- and intra-die process variation
Proceedings of the 2003 international symposium on Low power electronics and design
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose statistical sampling techniques in estimating the mean and distribution of full-chip leakage current under process variations. The stratified random sampling procedures are used to estimate the mean and variance of the full-chip leakage, under intra-die and inter-die process variations. Statistical quantile estimation method is then applied to estimate the cumulative distribution function. Experimental results show that, comparing to simple random sampling, the proposed approaches improve the estimation speed by 2.7X, on average.