ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Design of Deep Sub-Micron CMOS Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Proceedings of the 2003 international symposium on Low power electronics and design
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 international symposium on Low power electronics and design
Leakage current estimation of CMOS circuit with stack effect
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Proceedings of the 42nd annual Design Automation Conference
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Vector extraction for average total power estimation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
Variability-aware device optimization under ION and leakage current constraints
Proceedings of the 2006 international symposium on Low power electronics and design
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 44th annual Design Automation Conference
A novel charge recycling design scheme based on adiabatic charge pump
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip leakage current estimation based on statistical sampling techniques
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
A probabilistic technique for full-chip leakage estimation
Proceedings of the 13th international symposium on Low power electronics and design
Full custom low-power/high performance DDP-based Cobra-H64 cipher
Computers and Electrical Engineering
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Accurate estimation of vector dependent leakage power in the presence of process variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
SRAM CP: a charge recycling design schema for SRAM
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
Microelectronics Journal
| Hi-index | 0.00 |
Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Current models have been developed based on the exact device geometry, 2-D doping profile and operating temperature. A circuit level model of junction BTBT leakage (which is unprecedented) has been developed. Simple models of the subthreshold current and the gate current have been presented. Here, for the first time, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a Sum of Current Sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25nm effective length) at the room and at the elevated temperatures.