SRAM CP: a charge recycling design schema for SRAM

Authors:
Ka-Ming Keung;Akhilesh Tyagi
Affiliations:
Electrical and Computer Engineering, Iowa State University, Ames, IA;Electrical and Computer Engineering, Iowa State University, Ames, IA
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

An adiabatic charge-pump based charge recycling design was proposed in [1]. It was shown to save upto 15% energy on several DSP systems with no performance loss. In this paper, we illustrate new charge source multiplexing techniques that are especially targeted towards SRAM arrays. The trigger control mechanism for charge sharing, additionally, can be derived from the application level characteristics rather than from circuit level attributes. These two methods help minimize the charge sharing energy dissipation. The SPICE level simulation results show that the proposed scheme reduces energy consumption in L2 caches by 24.9% with no performance loss.