Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Leakage power modeling and reduction with data retention
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 40th annual Design Automation Conference
Implications of technology scaling on leakage reduction techniques
Proceedings of the 40th annual Design Automation Conference
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Estimation of Maximum Power-up Current
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Maximum Leakage Power Estimation for CMOS Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Peak Power Reduction in Low Power BIST
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ATS '01 Proceedings of the 10th Asian Test Symposium
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
Proceedings of the conference on Design, automation and test in Europe
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Scan Power Minimization through Stimulus and Response Transformations
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Experimental measurement of a novel power gating structure with intermediate power saving mode
Proceedings of the 2004 international symposium on Low power electronics and design
PFGASAT" A Genetic SAT Solver Combining Partitioning and Fuzzy Strategies
COMPSAC '04 Proceedings of the 28th Annual International Computer Software and Applications Conference - Volume 01
Rapid and Energy-Efficient Testing for Embedded Cores
ATS '04 Proceedings of the 13th Asian Test Symposium
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Exact and heuristic approaches to input vector control for leakage power reduction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor (CMOS) circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don't care bits (denoted by Xs) in test vectors to optimize leakage current in integrated circuit (IC) test by genetic algorithm. The techniques identify a set of don't care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector (MLV). Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage.